YuSynth Combined Sample & Hold with Noise generator
A bare double sided PCB (no need for the wire jumper links shown on the PCB layout) for the Yusynth S&H with Noise generator synth module. These PCBs are manufactured by Soundtronics with a percentage of the sale going to the creator of the YuSynth - Yves Usson. These are early days for the YuSynth Modular Synth at Soundtronics, our plan is to stock PCBs for all of the projects as well as components, kits and front panels. This is going to take time but will eventually be as comprehensive as our MFOS range.
No components are included with the PCB but check out our Synth Components section where you should find what you need. We do suggest visiting the YuSynth Noise + S&H project page for detailed information on both this PCB and the accompanying VC-Panner including Yves panel layouts but a summary is shown below.
Sorry but there is small error on the PCB. A track from the junction of R3 & R4 on the S&H side of the PCB should go to pin 3 of U1, not pin 2. This is easily corrected by cutting the track connection with pin 2 and solder a link from R4 to pin 3. The photo below shows this although you should carry this out after soldering in the components.
This single modules integrates two sub-modules : a noise voltage generator and a sample and hold (S&H) processor.
The noise generator generates three different signals : white noise (evenly distributed frequency spectrum), pink noise (1/f frequency spectrum, that is with a 3dB/octave slope), and a slow varying random voltage (frequency smaller than 6Hz).
The Sample and Hold processor has an internal clock but can be driven from an external clock. The clock rate ranges from 0.1Hz to 100Hz. The clock I/O acts either as an clock input or as a clock output depending on the position of the EXT/INT switch. A yellow LED shows the clock rate. A slew rate is also provided (its behaviour either linear or exponential can be selected with a jumper on the PCB).
As a default, the input of the S&H processor is connected to the white noise source.
Yves designed three different PCBs : a PCB that integrates both the noise generator and the S&H processor (this board 7220-046), a PCB for the noise generator on its own (7220-045) and a PCB for the S&H processor on its own (7220-030). Thus one can build the module of one's choice, either combined or separate.
The PCB can accept a choice of three types of power connector, it can be either a Synthesizers.com 6 pins MTA connector, a MOTM 4 pins MTA96 connector or a 10-pin Eurorack connector.
Separate supply rails are used for the two sub-modules. This was made necessary to solve an issue on the first prototype, the clock and trigger stages of the S&H were interfering with the noise amplifier stage of the noise generator!
Noise submodule : Q2 is connected as a reverse polarised diode in order to generate as much noise as possible. This noisy signal is first amplified by Q3 and routed both to U3b which amplifies the white noise signal and to Q4. A network or resistor-capacitors (R2-R24,C9-C11) shapes the spectrum. The result is a low-pass filtering with a 3dB/octave slope giving rise to the so-called pink noise. Then the pink noise is amplified by U3d which is followed by two low-pass filters to provide slow varying random voltages. The first filtering stage is second order low-pass with a cut-off frequency close to 5Hz the second stage provides a 6dB/octave lowpass with a cut-off frequency of 4.7Hz with some amplification in order to level up the random voltage.
Sample and Hold : U1 is an OPA in a classical astable multivibrator configuration, with the values of R3, R4, R5, C3 and P1 the slowest rate is 0.1Hz and fastest 10Hz. The positive part of the pulse is selected by D1 and routed to a switch that is used to toggle the S&H trigger between the internal clock and an external clock. Q1 drives a LED which flashes as a function of the clock rate. C4 differentiates the clock signal in order to convert the rising edge of the clock into a brief positive pulse (10ms). U2d is connected as a comparator. D2 selects the negative part of the pulse to drive the gate of the Q2 FET.
Click on the schematic thumbnail above for the circuit diagram.
The wiring schematic image in the above thumbnails show the panel wiring to the pots and sockets etc.
Setting and Trimming
The trimming is quite simple, it consists of taking a batch of BC547 transistors and selecting among these which one gives the highest white noise level while being symetrically balanced around 0V level, with the flatest spectrum. In order to do so, it is a good idea to use a transistor socket for Q2, this way one can swap easily the transistors to find the best one. It is a good practice to wait about 1min before checking the noise level and quality of white spectrum in order that Q2 has reached a steady temperature.
Below are the spectra Yves measured on the two boards he built. Some resistor values may also be adjusted to obtain the desired output levels.
The parts list below is direct from the YuSynth website. The value in the parts list is the default value and may differ to that quoted in the schematic / PCB silk image.
The parts list excludes knobs although we have standardised on the Cliff KM20B but it does include 1/4" jack sockets. All parts are available individually (use the part number in the search box above) or as a components kit that excludes sockets and knobs.
|C4||1n (any value between 1n and 10n will do)||7212-740||1|
|C5||100n Polyester Film||7212-718||1|
|C6||680n polyester film||7212-723||1|
|P1||500K reverse audio potentiometer (ALPHA)||7300-150||1|
|P2||1M log potentiometer||7300-070||1|
|Jk1,Jk5,k6||female jack socket||7212-203||3|
Noise Generator sub-module
|Q2*||BC547, *selected for maximum noise level and whitest spectrum||7212-490||1|
|C11||1n yellow LCC||7212-708||1|
|C10||3.3n yellow LCC||7212-711||1|
|C9||47n yellow LCC||7212-717||1|
|C16||150n yellow LCC||7212-719||1|
|C14,C15||1µF yellow LCC unpolarized||7212-724||2|
|Jk2,Jk3,Jk4||female jack socket||7212-203||3|